A first conventional method for operation of a PM DC brushless motor in all four quadrants of the motor torque versus motor speed diagram produces PWM voltage waveforms in a PWM motor controller wherein first, second and third half H-bridge transistor pairs conduct two at a time to generate waveforms to electronically commutate the motor. To produce a PWM duty cycle between 0% duty cycle and 100% duty cycle, the first conducting transistor pair is controlled with a PWM duty cycle equal to the desired duty cycle (DC) while the second conducting transistor pair is controlled such that either the upper transistor or the lower transistor conducts continuously. Current sensing for this implementation is accomplished using a current sensing element in series with at least 2 of the 3 half H-bridge motor outputs. This method requires multiple current sensing elements exposed to the PWM outputs of a PWM motor controller which adds cost and complexity to the motor controller.
A second conventional method for operation of a PM DC brushless motor in all four quadrants of the motor torque versus motor speed diagram produces PWM voltage waveforms in a PWM motor controller, shown in FIG. 1, wherein first, second and third half H-bridge transistor pairs conduct two at a time to generate voltage waveforms to electronically commutate the motor. There are six rotationally sequential commutation states, labeled left to right, wherein 101 denotes the first commutation state, 100 denotes the second commutation state, etc. The voltage waveforms applied to the windings of the first phase (arbitrarily labeled phase A), the second phase (arbitrarily labeled phase B), and the third phase (arbitrarily labeled phase C) are shown, wherein a particular transistor pair is assigned to a particular phase for a particular commutation state. Note that for each commutation state, one of the two voltage waveforms starts at the beginning of the PWM period and the other of the two voltage waveforms is delayed by ½ of the PWM period. A more detailed explanation of the operation of FIG. 1 is given below.
In this conventional method, the motor controller uses a single current sensing element in the DC bus and requires a minimum duty cycle for motor current sensing in order to properly sample the motor current. To produce a PWM duty cycle between the minimum duty cycle and 100% duty cycle, the first conducting transistor pair is controlled with a PWM duty cycle equal to the desired duty cycle (DC), which is greater than the minimum duty cycle, while the second conducting transistor pair is controlled such that either the upper transistor or the lower transistor conducts continuously. To produce a PWM duty cycle between 0% and the minimum duty cycle, both conducting transistor pairs must operate in a PWM mode. In this condition, the first conducting transistor pair is controlled with a PWM duty cycle equal to the minimum duty cycle plus the desired duty cycle (DCmin+DC) while the second conducting transistor pair is controlled with a PWM duty cycle equal to the minimum duty cycle (DCmin). It is noted that the widths of the waveforms in FIG. 1 are not drawn to scale. Under this condition the correct motor windings are effectively provided a positive voltage by the first conducting transistor pair and a negative voltage by the second conducting transistor pair during a single PWM period such that the sum of the voltages is equal to the desired duty cycle (DCmin+DC−DCmin=DC) which is effectively less than the minimum duty cycle (DCmin). In this implementation, the PWM duty cycle of the second conducting transistor pair is delayed from the first conducting transistor pair by a time equal to ½ of the PWM period. This allows the motor winding to average the applied positive and negative voltages and provides a symmetrical current waveform. This implementation requires the control electronics to reassign the PWM duty cycle delay for the second conducting transistor pair for each commutation of the motor windings. Some hardware or software implementations either cannot accommodate this reassignment or the accommodation is very difficult.
FIG. 1 illustrates a single PWM cycle timing of each of the 6 PM DC brushless motor commutation states for the conventional implementation. Under normal operating conditions, each of the 6 commutation states will contain repeated PWM periods. The number of repeated PWM periods will depend upon the rotational velocity of the motor. The 6 motor commutation states are represented by the binary combinations of 3 motor position sensor inputs and are defined as State 101, State 100, State 110, State 010, State 011, and State 001. A seventh state is shown at the right-most end of FIG. 1 which is a repeat of the left-most State 101.
Beginning with the left-most State 101, the conducting transistor Pair 1 is Phase A, and the conducting transistor Pair 2 is Phase B. The PWM duty cycle output on Phase A is the minimum duty cycle plus the requested duty cycle (DCmin+DC), and this occurs at the beginning of the PWM period. The PWM duty cycle output on Phase B is the minimum duty cycle (DCmin), and this output is delayed for ½ of the PWM period. The motor current is flowing in motor windings Phase A and Phase B in such a manner that the current flows from Phase A to Phase B.
At the first motor commutation time, the motor commutation state transitions to State 100. The conducting transistor Pair 1 remains Phase A, but the conducting transistor Pair 2 transitions to Phase C. The PWM duty cycle output on Phase A remains (DCmin+DC) at the beginning of the PWM period. The PWM duty cycle output on Phase C transitions to the minimum duty cycle (DCmin), and the output is delayed for ½ of the PWM period. The previous output on Phase C has not yet been discussed, but Phase C was last enabled in a previous State 001. During State 001, Phase C was set up as a conducting transistor Pair 1 with the output of (DCmin+DC) at the beginning of a PWM period. The transition to State 100 required Phase C to transition from a conducting transistor Pair 1 to a conducting transistor Pair 2. This transition required a PWM timing change for the Phase C PWM driver. The motor current is flowing in motor windings Phase A and Phase C in such a manner that the current flows from Phase A to Phase C.
At the second motor commutation time, the motor commutation state transitions to State 110. The conducting transistor Pair 2 remains Phase C, but the conducting transistor Pair 1 transitions to Phase B. The PWM duty cycle output on Phase C remains (DCmin) delayed for ½ of the PWM period. The PWM duty cycle on Phase B transitions to (DCmin+DC), and the output starts at the beginning of the PWM period. Phase B was last enabled in State 101 as a conducting transistor Pair 2 with the output of (DCmin) delayed for ½ of the PWM period. The transition to State 110 required Phase B to transition from a conducting transistor Pair 2 to a conducting transistor Pair 1. This transition required a PWM timing change for the Phase B PWM driver. The motor current is flowing in motor windings Phase B and Phase C in such a manner that the current flows from Phase B to Phase C.
At the third motor commutation time, the motor commutation state transitions to State 010. The conducting transistor Pair 1 remains Phase B, but the conducting transistor Pair 2 transitions to Phase A. The PWM duty cycle output on Phase B remains (DCmin+DC) at the beginning of the PWM period. The PWM duty cycle on Phase A transitions to (DCmin), and the output is delayed by ½ of the PWM period. Phase A was last enabled in State 100 as a conducting transistor Pair 1 with the output of (DCmin+DC) and the output at the beginning of the PWM period. The transition to State 010 required Phase A to transition from a conducting transistor Pair 1 to a conducting transistor Pair 2. This transition required a PWM timing change for the Phase A PWM driver. The motor current is flowing in motor windings Phase B and Phase A in such a manner that the current flows from Phase B to Phase A.
At the fourth motor commutation time, the motor commutation state transitions to State 011. The conducting transistor Pair 2 remains Phase A, but the conducting transistor Pair 1 transitions to Phase C. The PWM duty cycle output on Phase A remains (DCmin) delayed for ½ of the PWM period. The PWM duty cycle output on Phase C transitions to (DCmin+DC) at the beginning of the PWM period. Phase C was last enabled in State 110 as a conducting transistor Pair 2 with the output of (DCmin) and the output delayed by ½ of the PWM period. The transition to State 011 required Phase C to transition from a conducting transistor Pair 2 to a conducting transistor Pair 1. This transition required a PWM timing change for the Phase C PWM driver. The motor current is flowing in the motor windings Phase A and Phase C in such a manner that the current flows from Phase C to Phase A.
At the fifth motor commutation time, the motor commutation state transitions to State 001. The conducting transistor Pair 1 remains Phase C, but the conducting transistor Pair 2 transitions to Phase B. The PWM duty cycle output on Phase C remains (DCmin+DC) at the beginning of the PWM period. The PWM duty cycle output on Phase B transitions to (DCmin), and the output is delayed by ½ of the PWM period. Phase B was last enabled in State 010 as a conducting transistor Pair 1 with the output of (DCmin+DC) and the output at the beginning of the PWM period. The transition to State 001 required Phase B to transition from a conducting transistor Pair 1 to a conducting transistor Pair 2. This transition required a PWM timing change for the Phase B PWM driver. The motor current is flowing n motor windings Phase C and Phase B in such a manner that the current flows from Phase C to Phase B.
What is needed is an improved method for producing PWM voltage waveforms in a PWM motor controller of a PM DC brushless motor, such as, without limitation, a PWM motor controller of a PM DC brushless motor which uses a single current sensing element in the DC bus without requiring a PWM timing change of the PWM driver.